This invention relates to the field of integrated circuits. More particular, this invention relates to the forming of layouts for integrated circuits and the placement of vias between conductors within layouts of integrated circuits.
It is known to form layouts of integrated circuits using a library of standard cells and a system of tools responsive to both design rules for a target manufacturing process and a functional description of the integrated circuit to be formed (e.g. a registered transfer language (RTL) description of the integrated circuit) to form masks for use in manufacturing the integrated circuit. Typically the power grid to be used to provide power to the standard cells of the integrated circuit is set out during a floor planning stage of the integrated circuit synthesis. This power grid typically includes both the conductors and vias which belong to the power grid. These vias connect between power grid conductors in one layer and standard-cell power conductors in a different layer which connect the different portions of the standard cells to the power supply.
One of the design rules associated with a manufacturing process is a minimum via spacing requirement. In some processes this minimum via spacing requirement may correspond to a minimum via separation which is greater than the minimum separation between conductors (tracks/wires) which are used for power supply and signal routing. Thus, the minimum via spacing requirement can limit the freedom of position along a conductor at which a via may be placed due to the presence of vias within neighbouring conductors.